Job Title: Design Verification Engineer (DV)
Experience Required: 5 to 10 Years
Duration: 12 months
Job Location: (United States / Remote)
We are seeking an experienced Design Verification Engineer with a strong background in SoC/IP verification, particularly within the ARM ecosystem. The ideal candidate will possess a high level of expertise in System Verilog, UVM methodology, and functional/code coverage. In addition to technical acumen, solid communication and analytical skills are essential for customer interfacing and team collaboration.
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